1. Field of the Invention
The present invention relates generally to an integrated circuit and more particularly, to isolation between devices thereon.
2. Description of the Prior Art
FIG. 1 is a diagram showing a chip of a dynamic type semiconductor memory device as one example of a LSI.
Referring to FIG. 1, the chip comprises a memory array portion 21 and a peripheral circuit portion 22 such as sense amplifiers, decoders and the like.
FIG. 2 is a block diagram showing a whole structure of a dynamic type semiconductor memory device.
Referring to FIG. 2, the dynamic type semiconductor memory device comprises an array comprising a plurality of memory cells serving as a memory portion, a X decoder and a Y decoder for selecting each address thereof, and an input/output interface portion comprising a sense amplifier connected to an input/output buffer. A plurality of memory cells serving as a memory portion are each connected to intersection points of word lines connected to the X decoder and bit lines connected to the Y decoder, these word and bit lines constituting a matrix. The above-mentioned-array is thus implemented.
Next, an operation is described. The memory cell at an intersection point of the word line and the bit line is selected, when each of these lines is selected by the X decoder and the Y decoder in response to a row address signal and a column address signal externally provided, and information is read or written from or to the memory cell through the input/output interface portion comprising the sense amplifier and the input/output buffer.
Although discussion herein directs to the dynamic random access memory, the principles to be described hereinafter is applicable to other IC's obtaining different types of circuit regions as well.
In isolating between devices of the LSI such as the conventional dynamic type semiconductor memory device, a so-called LOCOS (Local Oxidation of Silicon: J. A. Appels et al Philips Res Rept 25 118 (1970)) structure is used.
The LOCOS isolation method has been used extensively since 1970's as the device isolation technology for semiconductor integrated circuit devices. However, the following difficulties have been raised as devices have become fine and a dimension thereof has been decreased to approximately 1 .mu..
FIG. 3A is a partial plan view showing a designed isolation region 500 and a designed active region Ri on a silicon substrate. FIGS. 3B and 3C are partial sectional views showing a device isolation technique by a selective oxidation method, taken along the line IIIB-IIIB in FIG. 3A.
(a) As shown in FIG. 3B, the field oxide film 501 makes encroachment under the silicon nitride film 3 (called bird's beaks) and a finished isolation width Wia is enlarged on both sides by Wb as compared with a designed isolation width Wid and, as a result, a portion of an active region that can be formed is reduced and it becomes difficult to form a fine device. Referring to FIG. 3A, the active region is reduced from a designed active region Ri to an actual active region Ra.
(b) As shown in FIG. 3C, because of a thermal treatment for the growth of the thick field oxide film 501, a p type impurity diffused region of the channel stopper region 4 is enlarged and a junction capacitance thereof with n type impurity diffused regions 23a and 23b is increased. In addition, in a MOS (Metal Oxide Semiconductor) transistor, a narrow channel effect in which a threshold voltage rises according to decrease of a channel width becomes noticeable.
(c) As shown in FIG. 3C, because the thick field oxide film 501 having a difference in level is formed in a region for isolation between devices, the surface of the isolation region becomes non-planar. This is inconvenient for formation of a fine pattern such as a wiring.
(d) Stress occurs between the thick field oxide film 501 and the silicon substrate 1 because of a thermal treatment for the growth of the thick field oxide film 501. This often brings about a crystalline defect such as stacking fault and the like in the silicon substrate 1.
In order to solve the above described difficulties, in place of the conventional LOCOS isolation method, a trench isolation technique is proposed which is described in "Deep Trench Isolated CMOS Devices" by R. D. Rung et al., International Electron Devices Meeting, 1982, Technical Digest, pp. 537. FIG. 3D is a partial plan view showing a designed isolation region 500 and an active region R on a silicon substrate. FIG. 3E is a partial sectional view showing a trench isolation structure, taken along the line IIIE--IIIE in FIG. 3D.
First, referring to the figures, in the trench isolation method, a trench is formed in a portion of the silicon substrate 1 serving as the isolation region by applying anisotropic etching such as reactive ion etching, using a pattern of a thick oxide film formed on the silicon substrate 1 as a mask. Boron (B.sup.+) is implanted in the trench, using the pattern on the thick oxide film as a mask and a channel stopper region 4 with high impurity concentration is formed in a portion of the silicon substrate 1 serving as the trench. A thin silicon oxide film is formed by applying thermal oxidation to the whole surface of the silicon substrate 1. An insulating material 502 such as silicon oxide is deposited over the whole surface such that the insulating material may fully fill in the trench, using the chemical vapor-deposition method and the like. Then, a photoresist is provided over the whole surface. Dry etching is made with the condition enabling an etching rate of the photoresist and that of the insulating material 502 to be equal, until the surface of the insulating material 502 is on the same level with the surface of the silicon substrate 1. As a result, the insulating material 502 is embedded inside the trench and a region for isolation between devices is formed with trench structure. Then, after a gate electrode 9 is formed through a gate oxide film on a portion serving as, for example, the channel region of the MOS transistor, n type impurity diffused regions 23a and 23b serving as the source region and the drain region, respectively, of the MOS transistor are formed.
However, in the trench isolation, it is difficult to introduce an impurity to a vertical sidewall of the trench by an ion implantation method widely used in general. As a result, a leakage current is liable to flow along the sidewall of the trench. In addition, because of the concentration of an electric field around the corner portion of the trench, an effect of a parasitic MOS transistor is easily generated and therefore, the leakage current is also liable to flow. In case that the concentration of an electric field occurs in the corner portions of the edge of the channel region, a threshold voltage is also liable to be decreased. Furthermore, stress occurs due to a difference between a coefficient of thermal expansion of the insulating material 502 filled in the trench and that of the silicon substrate 1. This often brings about a crystalline defect in the silicon substrate 1. Still another disadvantage is that the process of forming the trench isolations comprises complex steps as described above.
Because of the above described disadvantages, the trench isolation method needs many technological improvements and at the present, it is not widely used in manufacturing semiconductor integrated circuit devices.
Another means for solving problems of the bird's beak is proposed in U.S. Pat. No. 4,574,465, entitled "Differing Field Oxide Thickness in Dynamic Memory Device", filed Apr. 13, 1982. FIGS. 4A to 4E are diagrams showing a manufacturing method of the memory array portion and the peripheral circuit portion in the dynamic memory device shown therein. A silicon oxide film 2 is formed on both the memory array portion and the peripheral circuit portion on a main surface of a semiconductor substrate 1, a silicon nitride film 3 is formed on a predetermined position thereon and by using this as a mask, inversion preventing layers 4a and 4b are formed and film 5 for isolation between devices adjacent 4a and 4b are formed to be thinner than the oxide film in thickness of the conventional peripheral circuit portion. Then, a silicon nitride film 24 is formed on the whole memory array portion, and only the peripheral circuit portion is oxidized, whereby the thickness of the film for isolation between devices of the peripheral circuit portion is formed to have a conventional thickness. As described above, the length of the bird's beak of the memory array portion is decreased by making the oxide film for isolation between devices of the memory array portion of the dynamic type memory device thinner than the film for isolation between devices of the peripheral circuit portion.
There is no problem even if the thickness of the oxide film for isolation between devices made thinner in the memory array portion because an applied voltage at the memory array portion is lower than the applied voltage at the peripheral circuit portion. As a result, the thickness of the oxide film for isolation between devices of the memory array portion can be formed to be thinner than the thickness of the oxide film for isolation between devices of the peripheral circuit portion as described above.
A semiconductor memory device using the conventional trench isolation method has a problem that process becomes complicated because a trench is filled to be flattened. Furthermore, as the trench is formed on the silicon substrate, distortion is generated in the silicon substrate and leakage is likely to occur on an upper portion of the trench corner portion, which was also a problem.
In a method of changing the thickness of the conventional field oxide film, even if the thickness of the oxide film for isolation between devices was made thinner, the bird's beak would occur anyway, and because the inversion preventing layer is formed at both memory array portion and peripheral circuit portion simultaneously, the concentration of the inversion preventing layer can not be changed at the memory array portion and the peripheral circuit portion, with the result that the thickness of the oxide film for isolation between devices formed thereon can not be set arbitrarily.